Interview: German Chips Competence Centre (G3C) | The national interface to the European semiconductor ecosystem
Europe is facing the challenge of strengthening its technological resilience and global competitiveness in microelectronics, particularly in semiconductor development. To mitigate critical supply chain bottlenecks, reduce geopolitical risks, and keep pace with initiatives in the United States and China, the European Union launched the EU Chips Act in 2023. As part of this initiative, the German Chips Competence Centre (G3C) is now being established. As the national point of contact for innovators in semiconductor technologies, G3C connects stakeholders and facilitates targeted access to European pilot line infrastructures. In this interview, Project Manager Alexander Stanitzki explains how G3C operates as an independent coordinator, how cooperation within the European network of Chip Competence Centres is structured, and how this contributes to the implementation of the European semiconductor strategy.
Mr. Stanitzki, you lead the German Chips Competence Centre. Before going into details: what exactly is G3C and what role does it play?
The German Chips Competence Centre (G3C) is a project embedded in the EU Chips Act. It acts as the first national point of contact for all stakeholders seeking to initiate or implement new developments in chip and semiconductor technologies.
Our objective is to support innovation projects at an early stage in a structured way and to efficiently translate them into viable applications. To achieve this, we provide free advisory and matchmaking services for companies, start-ups, research institutions, and individuals. We initially assess the technical and economic feasibility of ideas and then connect them with suitable development and implementation partners, as well as with appropriate European infrastructures, in particular the pilot lines established under the EU Chips Act.
From a technological perspective, our focus is on chip design, process development, and integration, with particular emphasis on the heterogeneous integration of different technologies within a single device. In the long term, G3C contributes to strengthening Europe’s innovation capacity and technological sovereignty in the semiconductor sector. G3C is implemented by the Research Fab Microelectronics Germany (FMD).
You mentioned that the project is embedded in the EU Chips Act. How exactly is G3C integrated into this structure?
The EU Chips Act was adopted with the objective of strengthening the European semiconductor industry over the long term. It is structured around three pillars, with the first pillar focusing on the development and reinforcement of the European semiconductor ecosystem through targeted investments in research, development, and infrastructure.
A central element of this pillar is the establishment of European pilot lines, which provide the technological infrastructure. In parallel, the European Network of Chips Competence Centres (ENCCC) was created, currently comprising 30 centres in 28 countries. These centres are designed to support the transfer of innovative ideas into concrete implementation.
Because the individual Competence Centres operate in very different national contexts, the aCCCess project was initiated as an overarching framework. aCCCess defines harmonized working methods, common standards, and a coordinated public presence, ensuring consistency across Europe and enabling a truly pan-European perspective.
Why are there significantly more Chip Competence Centres than pilot lines in Europe, and how do these structures complement each other?
The European pilot lines represent thematically focused infrastructure investments, each addressing a specific technological domain such as heterogeneous integration, power electronics, photonics, or advanced logic technologies. It would be neither sensible nor necessary to establish this infrastructure in every European Member State.
At the same time, potential users of these pilot lines exist in all European countries. This is where the Chip Competence Centres play a key role. They act as national gateways into the European semiconductor ecosystem, providing local-language support, assessing needs, and directing stakeholders to the most appropriate pilot lines or suitable partners across Europe.
The close interconnection of the Competence Centres ensures transparency regarding available competencies and infrastructures across Europe and enables efficient cross-border referral of inquiries.
How is G3C positioned in relation to the European pilot lines, and in particular to the German APECS pilot line?
There are currently five European pilot lines: APECS, FAMES, NanoIC, PIXEurope, and WBG. The Competence Centres are not part of these pilot lines and are deliberately structured as independent entities.
Accordingly, G3C’s role is to act as a neutral information and referral partner within the European semiconductor ecosystem, directing inquiries to the most suitable pilot line or other appropriate partners based on technical and strategic criteria.
There is naturally a close professional connection to the APECS pilot line, as both APECS and G3C are implemented by the Research Fab Microelectronics Germany. This shared institutional background enables short communication paths and excellent insight into APECS’s services and access structures.
However, this does not affect our principle of neutrality. G3C does not favor any pilot line. We always recommend the infrastructure that best fits the specific technical and strategic requirements of a project. This also means that we work closely with other European Competence Centres to ensure that inquiries are evaluated in a well-founded manner and that realistic feasibility assessments can be provided.
Many other European Competence Centres are implemented by consortia. Why is G3C implemented by a single organization in Germany?
This is closely linked to the structure of the German microelectronics ecosystem. With FMD, Germany already has an established cross-institutional organization that bundles competencies from Fraunhofer and Leibniz institutes and provides a comprehensive overview of research, infrastructure, and expertise in micro- and nanoelectronics.
This structure allows G3C to be implemented centrally without the need to form a consortium, while still drawing on a large expert network in the background. This makes G3C both agile and operationally efficient.
What are the thematic priorities of G3C, and which target groups do you primarily address?
G3C focuses on three central areas along the semiconductor value chain: chip design, semiconductor process development, and integration, particularly the heterogeneous integration of different technologies within a single device, including the advanced packaging approaches required to enable this. These priorities reflect both current technological challenges and the strategic orientation of the European pilot lines.
On this basis, we support a wide range of application scenarios, including classical CMOS design, mixed-signal, high-frequency and photonics applications, as well as system-oriented approaches such as system-on-chip architectures and FPGA-based solutions. In process development, the spectrum ranges from 6- to 12-inch wafers across industrial and research-oriented application fields.
G3C addresses all stakeholders engaged in chip and semiconductor technologies or considering their use in applications. A particular focus is placed on start-ups and small and medium-sized enterprises (SMEs). Start-ups often require orientation and access to infrastructure and partners, while SMEs frequently have concrete innovation projects but lack in-house semiconductor or design expertise. In both cases, G3C supports the structured assessment of needs and identifies suitable technological and structural entry points into the European ecosystem.
How is the operational structure of G3C organized?
Each inquiry is assigned a dedicated contact person within the G3C team, who accompanies the entire process and remains the central point of contact throughout. This person coordinates all further steps, regardless of which institutions provide the required information or contributions.
In the background, G3C is supported by a network of experts from the participating institutes. Each institute has a designated responsible person, typically at management level, who has a comprehensive overview of available competencies and infrastructures. This structure enables targeted integration of expertise without fragmenting the user experience.
The workflow is clearly structured: G3C receives inquiries, conducts initial consultations, and clarifies fundamental technical questions. For more in-depth or highly specialized topics, requests are forwarded to the expert network for assessments, research, and technical feedback.
G3C’s services are free of charge. How is the Competence Centre funded?
G3C has a total budget of approximately €7.9 million over a four-year period. Funding is provided by the European Chips Joint Undertaking (Chips JU) and the German Federal Ministry of Research, Technology, and Space (BMFTR).
A small share of the budget is allocated to training and continuing education activities. The majority is dedicated to G3C’s core mission of advisory and matchmaking services.
Where do you currently see the biggest challenges?
At present, the team is still in the build-up phase, which naturally has an impact on daily operations. Maintaining equally intensive contact with all stakeholders while simultaneously supporting numerous events and projects is challenging given limited resources.
At the same time, this is also a strength of our approach. We are not a large consortium, but a comparatively small, agile team. This allows us to remain flexible, respond quickly, and actively shape structures together with the European network.
Another challenge is that many other Competence Centres and pilot lines are also still in their development phase. In some cases, concrete service offerings and responsibilities are still being established, which makes it difficult to provide definitive answers in all areas at this stage.
Finally, what makes the concept of the Chip Competence Centres globally unique from your perspective?
The uniqueness of the Chip Competence Centres lies in the combination of strong local roots and close Europe-wide networking. Each centre is deeply embedded in its national ecosystem while working in close coordination with other centres across Europe.
This structure enables inquiries to be handled efficiently at the local level and, when necessary, quickly referred to the most suitable partners or pilot lines across Europe. In addition, the centres are closely integrated with existing research and technology infrastructures, European pilot lines, and funding instruments such as the European Chip Design Platform.
The Competence Centres do not only facilitate access to infrastructure and expertise, but also actively support the financing and implementation of projects within a European framework.
Another key aspect is that all advisory and referral services are provided free of charge and are fully publicly funded. This allows even early-stage or unconventional ideas to be explored without immediate economic pressure. This combination of local proximity, European coordination, and free public support is, in my view, globally unique.
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